The major function of a telecommunications (xe2x80x9ctelcoxe2x80x9d) network device such as a switch, router or hybrid switch/router is to transfer network data or packets between various physical interfaces or ports on the network device. The ports are connected to external network attachments, for example, optical fibers, coaxial cables and twisted pair cables. Typically, a network device includes multiple forwarding cards (i.e., printed circuit boards or modules) coupled with the external network attachments through the physical interfaces. Network packets are transferred between forwarding cards through a switch fabric.
Typically, network devices transfer network data with other network devices over the external network attachments in accordance with the same clock signal (i.e., synchronously). The clock signal may be a Building Integrated Supply (BITS) Line supplied to both network devices or one network device may use a timing signal provided by the other network device over a network attachment. Regardless of which clock signal is used, a central timing subsystem with the network device is generally used to distribute timing reference signals to all cards and components involved in synchronous data transfer, for example, all port cards. It is crucial that components and cards within the network device transfer data according to the same synchronized timing signals, as transferring data at different times, even slightly different times, may lead to data corruption, the wrong data being sent and/or a network device crash. Distributing clock signals, therefore, must be done carefully to insure that the clock signal received by each component is not skewed with respect to the clock signals received by other components.
Since timing distribution is critical to network device operation, network devices often include redundant central timing subsystems. Redundancy, further complicates the distribution of timing reference signals and increases the potential for skew. In addition, if a failure of the primary central timing subsystem is detected such that a switch over to the secondary central timing subsystem is initiated, it is important that the components receiving the timing reference signals do not experience sudden phase shifts in the timing reference signals from the two central timing subsystems, as phase shifts and other noise on clock signals may also lead to data corruption or a network device crash.
Many network devices also use an independent clock signal to transfer data through the internal switch fabric, and again, a switch fabric central timing system is often used to distribute the timing reference signals to components and/or cards involved with data transfer through the switch fabric. In addition, in network devices with multiple processors, processor timing reference signals are often sent from a processor central timing system to each processor to allow the processors to synchronize their processes. Distributing multiple timing reference signals consumes considerable routing resources in the network device and again increases the likelihood of skew between clock signals.
The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) each having a voltage controlled timing circuit for receiving a constant master voltage signal and variable slave voltage signal. Each CTS also includes a control logic circuit for selecting the constant master voltage signal for use by the voltage controlled timing circuit when the CTS is master and for selecting the variable slave voltage signal when the CTS is slave. Using a constant master voltage signal eliminates the need for a separate master oscillator in each CTS. Oscillators are typically expensive, consume significant space on the printed circuit board and have location restrictions on where they may be placed on the printed circuit board.
In one aspect, the present invention provides a network device including a first central timing subsystem providing at least one first timing reference signal and at least one first master control signal, a second central timing subsystem providing at least one second timing reference signal and at least one second master control signal, where the first central timing subsystem receives the second timing reference signal and the second master control signal and the second central timing subsystem receives the first timing reference signal and the first master control signal and where the first central timing subsystem synchronizes the first timing reference signal to the second timing reference signal in accordance with the second master control signal and the second central timing subsystem synchronizes the second timing reference signal to the first timing reference signal in accordance with the first master control signal, and where the first central timing subsystem includes a voltage controlled timing circuit for generating the first timing reference signal, a constant master voltage signal connected to the voltage controlled timing circuit, a variable slave voltage signal connected to the voltage controlled timing circuit, and a control logic circuit connected to the voltage controlled timing circuit and the first and second master control signals, wherein the control logic circuit selects the constant master voltage signal for use by the voltage controlled timing circuit and generates a master state on the first master control signal when a slave state is detected on the second master control signal and wherein the control logic circuit selects the variable slave voltage signal for use by the voltage controlled timing circuit and generates the slave state on the first master control signal when the master state is detected on the second master control signal. The master state may be a logic one and the slave state may be a logic zero, or the master state may be a logic zero and the slave state may be a logic one. The voltage controlled timing circuit may be a first voltage controlled timing circuit, the constant master voltage signal may be a first constant master voltage signal, the variable slave voltage signal may be a first variable slave voltage signal and the control logic circuit may be a first control logic circuit and the second central timing subsystem may include a second voltage controlled timing circuit for generating the second timing reference signal, a second constant master voltage signal connected to the second voltage controlled timing circuit, a second variable slave voltage signal connected to the second voltage controlled timing circuit, and a second control logic circuit connected to the second voltage controlled timing circuit and the first and second master control signals, where the second control logic circuit selects the second constant master voltage signal for use by the second voltage controlled timing circuit and generates the master state on the second master control signal when the slave state is detected on the first master control signal and where the second control logic circuit selects the second variable slave voltage signal for use by the second voltage controlled timing circuit and generates the slave state on the second master control signal when the master state is detected on the first master control signal.
The first central timing subsystem may further receive a slot identification signal and the control logic circuit may cause the voltage controlled timing circuit to use one of the master and the slave voltage signals in accordance with the second master control signal and the slot identification signal. The voltage controlled timing circuit may include a voltage controlled crystal oscillator and may further include a multiplexor. The first central timing subsystem may also include a constant voltage circuit for providing the constant master voltage signal and may also include a phase locked loop circuit coupled to the first and second timing reference signals for providing the variable slave voltage signal. The first central timing subsystem may include a status detector for receiving the second timing reference signal and for providing a signal to the control logic circuit indicating a status of the second timing reference signal and the control logic circuit may cause the voltage controlled timing circuit to use the constant master voltage signal and the control logic circuit may provide the master state on the first master control signal when the signal indicates an invalid status for the second timing reference signal. The status detector may include an activity detector for providing an activity signal. The control logic circuit may cause the voltage controlled timing circuit to use the constant master voltage signal without software interaction.
The first central timing subsystem may also include a status detector for receiving the first timing reference signal and for providing a signal to the control logic circuit indicating a status of the first timing reference signal and the control logic circuit may cause the voltage controlled timing circuit to use the variable slave voltage signal and the control logic circuit may provide the slave state on the first master control signal when the signal indicates an invalid status for the first timing reference signal. The status detector may include an activity detector for providing an activity signal, and the control logic circuit may cause the voltage controlled timing circuit to use the variable slave voltage signal without software interaction. The phase locked loop circuit may provide an out of lock signal to the control logic circuit and the control logic circuit may cause the voltage controlled timing circuit to use the variable slave voltage signal and the control logic circuit may provide the slave state on the first master control signal when the out of lock signal indicates that the first and second timing reference signals are out of lock. The control logic may be coupled with a processor and the processor may be capable of controlling the control logic circuit to cause the control logic circuit to cause the voltage controlled timing circuit to use the constant master voltage signal and provide the master state on the first master control signal, and cause the voltage controlled timing circuit to use the variable slave voltage signal and provide the master state on the first master control signal.
In another aspect, the invention provides a method of operating a network device including providing a first timing reference signal from a first voltage controlled timing circuit connected to a first constant master voltage signal and a first variable slave voltage signal within a first central timing subsystem, providing a first master control signal from a first control logic circuit connected to the first voltage controlled timing circuit within the first central timing subsystem, providing a second timing reference signal from a second voltage controlled timing circuit connected to a second constant master voltage signal and a second variable slave voltage signal within a second central timing subsystem, providing a second master control signal from a second control logic circuit connected to the second voltage controlled timing circuit within the second central timing subsystem, synchronizing the second timing reference signal to the first timing reference signal in accordance with the first master control signal, and synchronizing the first timing reference signal to the second timing reference signal in accordance with the second master control signal. The method may also include detecting a slave status on the second master control signal, selecting the second variable slave voltage signal for use by the second voltage controlled timing circuit, selecting the first constant master voltage signal for use by first voltage controlled timing circuit, and generating a master status on the first master control signal. The method may also include detecting a master status on the second master control signal, selecting the second constant master voltage signal for use by the second voltage controlled timing circuit, selecting the first variable slave voltage signal for use by first voltage controlled timing circuit, and generating a slave status on the first master control signal.
Synchronizing the first timing reference signal to the second timing reference signal in accordance with the second master control signal may include detecting a value on the second master control signal indicating that the second central timing subsystem is performing as a slave central timing subsystem and selecting the first constant master voltage signal as an input to first voltage controlled timing circuit. The method may also include selecting the second variable slave voltage signal as an input to the second voltage controlled timing circuit. Synchronizing the first timing reference signal to the second timing reference signal includes detecting a value on the second master control signal indicating that the second central timing subsystem is performing as a master central timing subsystem and selecting the variable slave voltage signal as an input to the first voltage controlled timing circuit. The method may include selecting the second constant master voltage signal as an input to second voltage controlled timing circuit, and the method may include providing a first slot identifier, providing a second slot identifier, where synchronizing the second timing reference signal to the first timing reference signal is further in accordance with the second slot value and where synchronizing the first timing reference signal to the second timing reference signal is further in accordance with the first slot value. The method may include monitoring a status of the first timing reference signal and synchronizing the first timing reference signal to the second timing reference signal when the status indicates invalidity. In addition, the method may include providing a constant logic state on the first timing reference signal when the status indicates invalidity. The method may include removing the first central timing subsystem from the network device, detecting inactivity on the first timing reference signal, and providing the second constant master voltage signal to the second voltage controlled timing circuit, and the method may also include replacing the first central timing subsystem within the network device, detecting activity on the first timing reference signal and continuing to provide the second constant master voltage signal to the second voltage controlled timing circuit. The method may also include replacing the first central timing subsystem within the network device, detecting activity on the first timing reference signal, providing the first constant master voltage signal to the first voltage controlled timing circuit, and providing the second variable slave voltage signal to the second voltage controlled timing circuit.